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Philips Semiconductors Linear Products
Product specification
10-Bit P-compatible D/A converter
NE5020
DESCRIPTION
The NE5020 is a microprocessor-compatible monolithic 10-bit digital-to-analog converter subsystem. This device offers 10-bit resolution and 0.1% accuracy and monotonicity guaranteed over full operating temperature range. Low loading latches, adjustable logic thresholds, and addressing capability allow the NE5020 to directly interface with most microprocessor- and logic-controlled systems. The NE5020 contains internal voltage reference, DAC switches and resistor ladder. Also, the input buffer and output summing amplifier are included. In addition, the matched application resistors for scaling either unipolar or bipolar output values are included on a single monolithic chip. The result is a near minimum component count 10-bit resolution DAC system.
PIN CONFIGURATION
F, N Packages
DIGITAL GND DB0(LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7(MSB) 1 2 3 4 5 6 7 8 9 24 ANALOG GND 23 AMP COMP 22 SUM MODE 21 V CC+ 20 V OUT 19 VCC- 18 BIPOLAR OFFSET R 17 +V REFIN 16 -VREFIN 15 VREFOUT 14 V REFADJ 13 LE2
NC 10 11 LE1 12
FEATURES
* 10-bit resolution * Guaranteed monotonicity over operating range * 0.1% relative accuracy * Unipolar (0V to +10V) and bipolar ( 5V) output range * Logic bus compatible * 5s settling time
APPLICATIONS
* Precision 10-bit D/A converters * 10-bit analog-to-digital converters * Programmable power supplies * Test equipment * Measurement instruments
ORDERING INFORMATION
DESCRIPTION 24-Pin Ceramic Dual In-Line Package (CERDIP) 24-Pin Plastic Dual In-Line Package (DIP) TEMPERATURE RANGE 0 to 70C 0 to 70C ORDER CODE NE5020F NE5020N DWG # 0588B 0412A
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853-0392 13721
Philips Semiconductors Linear Products
Product specification
10-Bit P-compatible D/A converter
NE5020
BLOCK DIAGRAM
(11) DB9 MSB (10) DB8 (9) DB7 (8) DB6 (7) DB5 (6) DB4 (5) DB3 (4) DB2 (3) DB1 (2) DB0 LSB
(13) LE2
LATCHES AND SWITCH DRIVERS
(12) LE1
SUM (22) NODE (1) DIGITAL GND (21) +VCC VREF (15) OUT VREF (14) ADJ (17) +VREF IN (18) BIPOLAR OFFSET (16) -VREF IN RREF RBIP + - QR Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 QT INT VREF DAC SWITCHES DAC OUTPUT CURRENT Rfb - +
VOUT (20)
R
AMP (23) COMP ANALOG (24) GND
R
-VCC (19)
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC+ VCCVIN VREF IN VREF ADJ VSUM IREFSC IOUTSC PD Positive supply voltage Negative supply voltage Logic input voltage Voltage at +VREF input Voltage at VREF adjust Voltage at sum node Short-circuit current to ground at VREF OUT Short-circuit current to ground or either supply at VOUT Maximum power dissipation TA=25C, F package N package TA TSTG TSOLD Operating temperature range NE5020 Storage temperature range Lead soldering temperature (10 sec. max) (still-air)1 2150 2150 0 to +70 -65 to +150 300 mW mW C C C PARAMETER RATING 18 -18 0 to 18 12 0 to VREF 12 Continuous Continuous UNIT V V V V V V
NOTES: 1. Derate above 25C at the following rates: F package at 17.2mW/C N package at 17.2mW/C
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Philips Semiconductors Linear Products
Product specification
10-Bit P-compatible D/A converter
NE5020
DC ELECTRICAL CHARACTERISTICS
VCC+=+15V, VCC-=-15V, 0 TA70C, unless otherwise specified.1 Typical values are specified at 25C. SYMBOL PARAMETER Resolution Monotonicity Relative accuracy VCC+ VCCVIN(1) VIN(0) IIN(1) IIN(0) VFS +VFS -VFS Positive supply voltage Negative supply voltage Logic "1" input voltage Logic "0" input voltage Logic "1" input current Logic "0" input current Full-scale output Full-scale output Negative full-scale Pin 1=0V Pin 1=0V Pin 1=0V, 2NOTES: 1. Refer to Figure 1.
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Philips Semiconductors Linear Products
Product specification
10-Bit P-compatible D/A converter
NE5020
DC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL VZS IOS PSR+(OUT) PSR-(OUT) TCFS TCZS IREF2 IREF SC PSR+REF PSR-REF VREF TCREF ZIN ICC+ ICC PD PARAMETER Zero-scale output Output short-circuit current Output power supply rejection (+) Output power supply rejection (-) Full-scale temperature coefficient Zero-scale temperature coefficient Reference output current Reference short circuit current Reference power supply rejection (+) Reference power supply rejection (-) Reference voltage Reference voltage temperature coefficient DAC VREF IN input impedance Positive supply current Negative supply current Power dissipation TA=25C VREF OUT=0V V-=-15V, 13.5VV+16.5V, IREF=1.0mA V+=15V, -13.5VV-16.5V, IREF=1.0mA, TA=25C IREF=1.0mA IREF=1.0mA VCC+=15V VCC -=-15V IREF=1.0mA, VCC=15V 4.9 15 .003 .003 5.0 60 5.0 7 -10 255 14 -15 435 TEST CONDITIONS Unipolar mode, VREF=5.000V, all bits low, TA=25C TA=25C VOUT=0V V-=-15V, 13.5VV+16.5V, external VREF IN=5.000V V+=15V, -13.5VV--16.5V, external VREF IN=5.000V VREF IN=5.000V LIMITS Min -30 15 0.001 0.001 20 5 3 30 .01 .01 5.25 Typ Max +30 40 0.01 0.01 UNIT mV mA %FS/ %VS %FS/ %VS ppmFS /C ppmFS/C mA mA %VR/ %VS %VR/ %VS V ppm/C k mA mA mW
NOTES: 1. Refer to Figure 1. 2. For IREF OUT greater than 3mA, an external buffer is required.
AC ELECTRICAL CHARACTERISTICS1
VCC = +15V, TA = 25C. SYMBOL tSLH tSHL tPLH tPHL tPLSB tPLH tPHL tS tH tPW PARAMETER Settling time Settling time Propagation delay Propagation delay Propagation delay Propagation delay Propagation delay Set-up time Hold time Latch enable pulse width TO 1/2LSB 1/2LSB Output Output Output Output Output LE Input FROM Input Input Input Input Input LE LE Input LE TEST CONDITIONS All bits low-to-high2 All bits high-to-low3 high-to-low3 All bits switched low-to-high2 All bits switched 1 LSB change2,3 Low-to-high transition4 High-to-low transition5
1,6 1,6 1,6
LIMITS Min Typ 5 5 30 150 150 300 150 100 50 150 Max
UNIT s s ns ns ns ns ns ns ns ns
NOTES: 1. Refer to Figure 2. 2. See Figure 5. 3. See Figure 6. 4. See Figure 7. 5. See Figure 8. 6. See Figure 9.
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Philips Semiconductors Linear Products
Product specification
10-Bit P-compatible D/A converter
NE5020
LE2 LE1
MSB
LSB
VCC+ 0.47F
LE2 LE1
MSB
LSB
VCC+ 0.47F
5.000V
11 10 9 8 7 6 5 4 3 2 12 13 17 VREF IN 15 VREF OUT 14 5020
21 DIG GND 1 ANA GND 24 -VREF IN 16 VOUT 20 SUM 22 AMP 23 COMP OUTPUT 30pF 5k
11 10 9 8 7 6 5 4 3 2 12 13 17 15 14 5020
21 DIG GND 1 ANA GND 24 -VREF IN 16 VOUT 20 SUM 22 AMP 23 COMP OUTPUT 30pF 5k 100pF
19 100pF
18
19
18
0.1F 0.1F VCC- VCC-
Figure 1. DC Parametric Test Configuration
MSB LSB VCC+
Figure 2. AC Parametric Test Configuration
LE2 LE1
0.47F
11 10 9 8 7 6 5 4 3 2 12 13 17 VREF IN 15 VREF OUT 10k 10T 80k 14 VREF ADJ 5020
21 DIG GND 1 ANA GND 24 -VREF IN 16 VOUT 20 SUM 22 AMP 23 COMP OUTPUT
30pF
5k 100pF
FULL SCALE ADJUST
19
18
0.1F VCC-
VCC+ 1M 20k 10T VCC- ZERO SCALE ADJUST
Figure 3. Full-/Zero-Scale Adjust -- Unipolar Output (0-10V)
VCC+ 0.47F
LE2 LE1
MSB
LSB
11 10 9 8 7 6 5 4 3 2 12 13 17 VREF IN 15 VREF OUT 10k 10T 80k BIP OFF 18 14 VREF ADJ 5020
21 DIG GND 1 ANA GND 24 -VREF IN 16 VOUT 20 SUM 22 AMP 23 COMP OUTPUT
30pF
5k 100pF
19
0.1F VCC-
VCC+ 1M 20k 10T VCC- FULL SCALE ADJUST
Figure 4. Bipolar Output Operation (-5 to +5V)
August 31, 1994
761
Philips Semiconductors Linear Products
Product specification
10-Bit P-compatible D/A converter
NE5020
DATA
DATA
tSLH 10V tPLH OUTPUT 1LSB
LE
0V LE = LOW
10V OUTPUT 0V
Figure 5. Settling Time and Propagation Delay, Low-to-High Data
Figure 8. Propagation Delay, Latch Enable to Output
DATA tMIN
tSHL 10V
tS
th
OUTPUT
DATA 0V LE = LOW 1LSB
Figure 6. Settling Time and Propagation Delay, High-to-Low Data
Figure 9. Latch Enable Pulse Width, Setup and Hold Times
DATA
LE
tPLH 10V OUTPUT 0V
Figure 7. Propagation Delay, Latch Enable to Output
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tPHL
LE
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tPHL
tPHL
EEEE EEEE EEEE EEEE
Philips Semiconductors Linear Products
Product specification
10-Bit P-compatible D/A converter
NE5020
TTL, DTL VTH = +1.4V
VTH = VPIN1 + 1.4V +15V CMOS, HTL, HNIL VTH = +7.6V +12V TO +15V +15V 9.1k
PMOS VTH = 0V
NE5020 10k DIG GND (PIN 1) 6.2V ZENER PIN 1 6.2k
IN4148 PIN 1 0.1F 10k -5V TO -10V NOTE: DO NOT EXCEED NEGATIVE LOGIC INPUT RANGE OF DAC +5V CMOS VTH = +2.8V +5V +10V 3.6k PIN 1 6.2k PIN 1 3.6k 0.1F 3.9k 1k 1.3k 2N3904 IN4148 PIN 1 +10V CMOS VTH = +9.0V 10k ECL VTH -1.29V PIN 1
IN4148
Figure 10.
CIRCUIT DESCRIPTION
The NE5020 provides ten data latches, an internal voltage reference, application resistors, and a scaled output voltage in addition to the basic DAC components (see Block Diagram).
10 details several bias schemes used to provide the proper threshold voltage levels for various logic families. To be compatible with a bus-oriented system, the DAC should respond in as short a period as possible to insure full utilization of the microprocessor, controller and I/O control lines. Figure 9 shows the typical timing requirements of the latch and data lines. This figure indicates that data on the data bus should be stable for at least 50ns after LE is changed to a high state. The independent LE (LE1 and LE2) lines allow for direct interface from an 8-bit bus (see Figure 11). Data for the two MSBs is supplied and stored when LE2 is activated low and returned high according to the NE5020 timing requirements. Then LE1 is activated low and the remaining eight LSBs of data are transferred into the DAC. With LE1 returning high, the loading of 10-bit data word from an 8-bit data bus is complete. Occasionally the analog output must change to its data value within one data address operation. This is no problem using the NE5020 on a 16-bit bus or any other data bus with 10 or greater data bits. This can be accomplished from an 8-bit data bus by utilizing an external latch circuit to pre-load the two MSB data values. Figure 12 shows the circuit configuration. After pre-loading (via LE pre-load) the external latch with the two MSB values, LE2 is activated low and the eight LSBs and the two MSBs are concurrently loaded into the DAC in one address operation. This permits the DAC output to make its appropriate change at one time.
Latch Circuit
Digital interface with the NE5020 is readily accomplished through the use of two latch enable ports (LE1 and LE2) and ten data input latches. LE2 controls the two most significant bits of data (DB9 and DB8) while LE1 controls the eight lesser significant bits (DB7 through DB0). Both the latch enable ports (LE) and the data inputs are static- and threshold-sensitive. When the latch enable ports (LE) are high (Logic `1') the data inputs become very high impedances and essentially disappear from the data bus. Addressing the LE with a low static (Logic `0'), the latches become active and adapt the logic states present on the data bus. During this state, the output of the DAC will change to the value proportional to the data bus value. When the latch enable returns to a high state, the selected set of data inputs (i.e., depending on which LE goes high) `memorizes' the data bus logic states and the output changes to the unique output value corresponding to the binary word in the latch. The data inputs are inactive and high impedance (typically requiring -2A for low (0.8V max) or 0.1A for high (2.0V min) when the LE is high. Any changes on the data bus with LE high will have no effect on the DAC output. The digital logic inputs (LE and DB) for the NE5020 utilize a differential input logic system with a threshold level of +1.4V with respect to the voltage level on the digital ground pin (Pin 1). Figure
August 31, 1994
763
Philips Semiconductors Linear Products
Product specification
10-Bit P-compatible D/A converter
NE5020
B0
DATA BUS B6 B7
DB 9 MSB
8
7
6
5
4
3
2
1
0 LSB
LE2 LE1
LATCHES
LATCHES
DAC
OUTPUT
Figure 11. NE5020 P Interface 8-Bit Data Bus Example
8-BIT DATA BUS +5V
1 4 10 13 3 LE PRE-LOAD INVERTER
2 74LS74 11 5 12 9
11 MSB
10
9
8
7
6
5
4
3
2 LSB 20
LE LOAD
12 13 NE5020
Figure 12. Pre-loading the 2 MSBs to Provide a Single-Step Output
August 31, 1994
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Philips Semiconductors Linear Products
Product specification
10-Bit P-compatible D/A converter
NE5020
VREF IN (17) IREF 5k
5k
+ To R-2R Ladder (16) BIPOLAR OFFSET (18) JUMPER FOR BIPOLAR OPERATION SUM NODE (22) - DAC AMP
VCC (ID IREF) 5k
ID
DAC CURRENT FROM CURRENT SWITCHES
-
+ OUTPUT AMP
Figure 13. Bipolar Output
Reference Interface
The NE5020 contains an internal bandgap voltage reference which is designed to have a very low temperature coefficient and excellent long-term stability characteristics. The internal bandgap reference (1.23V) is buffered and amplified to provide the 5V reference output. Providing a VREF ADJ (Pin 14) allows trimming of the reference output. Utilization of the adjust circuit shown in Figure 15 performs not only VREF adjustment, but also full-scale output adjust. Notice that the VREF ADJ pin is essentially the sum node of an op amp and is sensitive to excessive node capacitance. Any capacitance on the node can be minimized by placing the external resistors as close as possible to the VREF ADJ pin and observing good layout practices. The VREF OUT node can drive loads greater than the DAC VREF input requirements and can be used as an excellent system voltage reference. However, to minimize load effects on the DAC system accuracy, it is recommended that a buffer amplifier be used.
I OUT +
2V REF R REF
DB9 DB8 DB7 ) ) ) 2 4 8
DB5 DB3 DB6 DB4 ) ) ) ) 32 64 128 16 DB0 DB2 DB1 ) ) 256 512 1024 Because of the fixed internal compensation of the reference amp, the slew rate is limited to typically 0.7V/s and source impedance at the VREF INPUT greater than 5k should be avoided to maintain stability. The -VREF INPUT pin is uncommitted to allow utilization of negative polarity reference voltages. In this mode +VREF INPUT is grounded and the negative reference is tied directly to the -VREF INPUT contains a 5k resistor that matches a like resistor in the +VREF INPUT to reduce voltage offset caused by op amp input bias currents.
Output Amplifier and Interface
The NE5020 provides an on-chip output op amp to eliminate the need for additional external active circuits. Its two-stage design with feed-forward compensation allows it to slew at 15V/s and settle to within 1/2LSB in 5s. These times are typical when driving the rated loads of RL 5k and CL 50pF with recommended values of CFF = 1nF and CFB = 30pF. Typical input offset voltages of 5mV and 50k open-loop gain insure that an accurate current-to-voltage conversion is performed when using the on-chip RFB resistor. RFB is matched to RREF and RBIP to maintain accurate voltage gain over operating conditions. The diode shown from ground to sum node prevents the DAC current switches from saturating the op amp during large signal transitions which would otherwise increase the settling time. The output op amp also incorporates output short circuit protection for both positive and negative excursions. During this fault condition IOUT will limit at 15mA typical. Recovery from this condition to rated accuracy will be determined by duration of short-circuit and die temperature stabilization.
Input Amplifier
The DAC reference amplifier is a high gain internally-compensated op amp used to convert the input reference voltage to a precision bias current for the DAC ladder network. The Block Diagram details the input reference amplifier and current ladder. The voltage-to-current converter of the DAC amp will generate a 1mA reference current through QR with a 5V VREF. This current sets the input bias to the ladder network. Data bit 9 (DB9)(Q9), when turned on, will mirror this current and will contribute 1mA to the output. DB8 (Q8) will contribute 1/2 of that value or 0.5mA, and so on. These current values act as current sinks and will add at the sum node to produce a DAC ladder to sum node function of:
August 31, 1994
765
Philips Semiconductors Linear Products
Product specification
10-Bit P-compatible D/A converter
NE5020
R1 = 20K, 10T POTENTIOMETER VCC -VCC
R2 = 1M
SUM NODE 5k DAC CURRENT OUTPUT
(22)
(OPTIONAL)
- + 5k AMP COMP (23)
VOUT
(20)
CFF
(24)
CC
Figure 14. Zero-Scale Adjustment
VREF OUT VREF OUT (15) 15k R3 = 80k R3 = 10k 10T POT VREF ADJ (14) 5k
+
INT REF
-
Figure 15. Reference Adjust Circuit potentiometer R1 until VOUT equals 0.000V in the unipolar mode or -5.000V in the bipolar mode (see bipolar section accomplishes this The NE5020 includes a thermally matched resistor, RBIP, to offset trim. the output voltage by 5V to obtain -5V to +5V output voltage range operation. This is accomplished by shorting Pins 18 and 22 (see Full-Scale Adjustment Figure 13). This connection produces a current equal to (VREFIN - A recommended full-scale adjustment circuit, when using the SUM NODE) / RBIP (1mA nominal), which is injected into the sum internal voltage reference, is shown in Figure 15. Potentiometer R3 node. Since full-scale current out is approximately 2mA is adjusted until VOUT equals 9.99023V. In many applications where (1.9980mA), (2mA - 1mA)5k = 5V will appear at the output. For the absolute accuracy of full-scale is of low importance when zero DAC output currents, 1mA is still injected into sum node and compared to the other system accuracy factors this adjustment VOUT = -(5k) (1mA) = -5V. Zero-scale adjust and full-scale adjust circuit is optional. are performed as described below, noting that full-scale voltage is
Bipolar Output Voltage
now approximately +5V. Zero-scale adjust may be used to trim VOUT = 0.00 with the MSB high or VOUT = -5.0V with all bits off.
Zero-Scale Adjustment
The method of trimming the small offset error that may exist when all data bits are low is shown in Figure 14. The trim is the result of injecting a current from resistor R2 that counteracts the error current. Adjusting
As resistors RREF, RFB, and RBIP shown in the Block Diagram are integrated in close proximity, they match and track in value closely over wide ambient temperature variations. Typical matching is less than 0.3% which implies that typical full-scale (or gain) error is less than 0.3% of ideal full-scale value.
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